This invention relates, in general, to buffer circuits, and more particularly, to clocked buffer circuits.
In a complex integrated circuit such as a microcomputer or a circuit which is to interface with a microcomputer there are strict timing controls for receiving and transmitting various data and control signals. In modern circuits there is normally only a single 5 volt power supply available. Particularly in circuits designed in a single channel MOS technology, for example NMOS, there is a problem with maintaining sufficient signal levels for the generation and timing of all the required signals. This is due primarily to the 0.6 to 1.2 threshold voltage of NMOS enhancement transistors. The use of depletion and natural transistors with threshold voltages of -1.1 to -1.4 and 0.0 to 0.4, respectively, have been found to be helpful in this regard. Due to power restraints and restraints on available chip area, natural and depletion devices must be used judiciously.
Various bootstrap techniques have been developed to retain signal levels at 5 volts while also retaining a large amount of power. One of the simplest techniques is a self-bootstrapping transistor. A control signal is applied to a control electrode of a transistor. Subsequently a full power supply timing signal is applied to a first current electrode. If the control signal is a logic high near 5 volts, for example 3 to 4 volts, the occurrence of the timing signal will cause the voltage of the control electrode to be raised well above 5 volts due to the capacitive coupling between the first current electrode and the control electrode. This allows the full signal strength of the timing signal to be coupled to a second current electrode of the transistor. Consequently, the self-bootstrapping transistor provides a full power supply signal of 5 volts as an output on its second current electrode in response to the control signal being a logic high and the occurrence of the timing signal. When the control signal is a logic low at ground potential, the control electrode of the transistor is held to ground so that the transistor will not turn on. Consequently, the timing signal is not coupled to the second current electrode. Accordingly, an output is provided which correlates to the control signal upon the occurrence of the timing signal.
This is a useful technique for providing a clocked output when the output is to be the same duration as the timing signal. For the case when the control signal is a logic high, the timing signal switching from a logic high to a logic low causes the output to also to switch to a logic low because the self-bootstrapping transistor is still turned on. This problem has been partially solved for clock drivers where the output is simply to occur for every occurrence of the timing signal by using a precharge signal and the removal thereof on the control electrode of the self-bootstrapping transistor in response to the timing signal. Other solutions involve using source-follower techniques which may additionally involve a bootstrap action with a capacitor connected between a gate and a source.